 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? 2004 microchip technology inc. ds39622a-page 1 pic18fx5x5/x6x0 1.0 device overview this document includes the programming specifications for the following devices: 2.0 programming overview of the pic18fx5x5/x6x0 pic18fx5x5/x6x0 devices can be programmed using either the high-voltage in-circuit serial programming tm (icsp tm ) method, or the low-voltage icsp method. both methods can be done with the device in the users? system. the low-voltage icsp method is slightly different than the high-voltage method and these differ- ences are noted where applicable. this programming specification applies to pic18fx5x5/x6x0 devices in all package types. 2.1 hardware requirements in high-voltage icsp mode, pic18fx5x5/x6x0 devices require two programmable power supplies: one for v dd and one for mclr /v pp . both supplies should have a minimum resolution of 0.25v. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? for additional hardware parameters. 2.1.1 low-voltage icsp programming in low-voltage icsp mode, pic18fx5x5/x6x0 devices can be programmed using a v dd source in the operating range. the mclr /v pp does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? for additional hardware parameters. 2.2 pin diagrams the pin diagrams for the pic18fx5x5/x6x0 family are shown in figure 2-1 and figure 2-2. table 2-1: pin descriptions (during programming): pic18fx5x5/x6x0 pic18f2515 pic18f4515 pic18f2525 pic18f4525 pic18f2585 pic18f4585 pic18f2610 PIC18F4610 pic18f2620 pic18f4620 pic18f2680 pic18f4680 pin name during programming pin name pin type pin description mclr /v pp /re3 v pp p programming enable v dd (2) v dd p power supply v ss (2) v ss pground rb5 pgm i low-voltage icsp input when lvp configuration bit equals ? 1 ? (1) rb6 pgc i serial clock rb7 pgd i/o serial data legend: i = input, o = output, p = power note 1: see section 5.3 ?single-supply icsp programming? for more detail. 2: all power supply (v dd ) and ground (v ss ) must be connected. flash microcontroller pr ogramming specification
pic18fx5x5/x6x0 ds39622a-page 2 ? 2004 microchip technology inc. figure 2-1: pic18fx5x5/x6x0 family pin diagrams rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 rb3/ccp2 (1) /an9 rb2/int2/an8 rb1/int1/an10 rb0/int0/flt0/an12 v dd v ss rd7/psp7/p1d rd6/psp6/p1c rd5/psp5/p1b rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1/p1a rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f4515/4525 40-pin pdip (600 mil) pic18f2515/2525 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out v ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 rb3/ccp2 (1) /an9 rb2/int2/an8 rb1/int1/an10 rb0/int0/an12 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda 28-pin sdip, soic (300 mil) note 1: pin feature is dependent on device configuration. PIC18F4610/4620 PIC18F4610/4620 note 1: pin feature is dependent on device configuration. ? 2004 microchip technology inc. ds39622a-page 3 pic18fx5x5/x6x0 figure 2-2: pic18fx5x5/x6x0 family pin diagrams 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4515/4525 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref - ra1/an1 ra0/an0 mclr /v pp /re3 nc rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1/p1a rc1/t1osi/ccp2 (1) nc nc rc0/t1oso/t13cki osc2/clko/ra6 osc1/clki/ra7 v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss /lvdin/c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c v ss v dd rb0/int0/flt0/an12 rb1/int1/an10 rb2/int2/an8 rb3/ccp2 (1) /an9 44-pin tqfp rd7/psp7/p1d 5 4 PIC18F4610/4620 44-pin qfn pic18f4515/4525 ra3/an3/vref+ ra2/an2/vref-/cvref- ra1/an1 ra0/an0 mclr /v pp /re3 rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an11 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1/p1a rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki osc2/clko/ra6 osc1/clki/ra7 v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss /lvdin/c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c v ss v dd rb0/int0/flt0/an12 rb1/int1/an10 rb2/int2/an8 rb3/ccp2 (1) /an9 rd7/psp7/p1d v ss v dd v dd PIC18F4610/4620 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 5 4 note 1: pin feature is dependent on device configuration. note 1: pin feature is dependent on device configuration. pic18fx5x5/x6x0 ds39622a-page 4 ? 2004 microchip technology inc. figure 2-3: pic18fx585/x680 family pin diagrams pic18f2585 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin vss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t13cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an9 rb3/canrx rb2/int2/cantx rb1/int1/an8 rb0/int0/an10 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda 28-pin sdip, soic (300 mil) pic18f2680 rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an9 rb3/canrx rb2/int2/cantx rb1/int1/an8 rb0/int0/flt0/an10 v dd v ss rd7/psp7/p2d rd6/psp6/p2c rd5/psp5/p2b rd4/psp4/ccp2/p2a rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3/c2ina rd2/psp2/c2inb mclr /v pp /re3 ra0/an0/cv ref ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin re0/rd /an5 re1/wr /an6/c1out re2/cs /an7/c2out v dd v ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t13cki rc1/t1osi rc2/ccp1 rc3/sck/scl rd0/psp0/c1inb rd1/psp1/c1ina 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f4585 40-pin pdip (600 mil) pic18f4680 ? 2004 microchip technology inc. ds39622a-page 5 pic18fx5x5/x6x0 figure 2-4: pic18fx585/x680 family pin diagrams 44-pin qfn 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4585 37 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0/cv ref - mclr /v pp /re3 rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an9 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3/c2ina rd2/psp2/c2inb rd1/psp1/c1ina rd0/psp0/c1inb rc3/sck/scl rc2/ccp1 rc1/t1osi rc0/t1oso/t13cki osc2/clko/ra6 osc1/clki/ra7 v ss av dd e2/cs /an7/c2out re1/wr /an6/c1out re0/rd /an5 ra5/an4/ss /lvdin ra4/t0cki rc7/rx/dt rd4/psp4/ccp2/p2a rd5/psp5/p2b rd6/psp6/p2c v ss v dd rb0/int0/flt0/an10 rb1/int1/an8 rb2/int2/cantx rb3/canrx rd7/psp7/p2d 5 4 v ss v dd v dd pic18f4680 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4585 37 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0/cv ref mclr /v pp /re3 nc rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/kbi0/an9 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3/c2ina rd2/psp2/c2inb rd1/psp1/c1ina rd0/psp0/c1inb rc3/sck/scl rc2/ccp1 rc1/t1osi nc nc rc0/t1oso/t13cki osc2/clko/ra6 osc1/clki/ra7 v ss v dd re2/cs /an7/c2out re1/wr /an6/c1out re0/rd /an5 ra5/an4/ss /lvdin ra4/t0cki rc7/rx/dt rd4/psp4/ccp2/p2a rd5/psp5/p2b rd6/psp6/p2c v ss v dd rb0/int0/flt0/an10 rb1/int1/an8 rb2/int2/cantx rb3/canrx 44-pin tqfp rd7/psp7/p2d 5 4 pic18f4680 pic18fx5x5/x6x0 ds39622a-page 6 ? 2004 microchip technology inc. 2.3 memory map the code memory space extends from 0000h to 0ffffh (64 kbytes) in four 16-kbyte blocks. addresses 0000h through 07ffh, however, define a ?boot block? region that is treated separately from block 0. all of these blocks define code protection boundaries within the code memory space. table 2-2: implementation of code memory figure 2-5: memory map and the code memory space for pic18fx5x5/x6x0 devices device code memory size (bytes) pic18f2515 000000h-00bfffh (48k) pic18f2525 pic18f2585 pic18f4515 pic18f4525 pic18f4585 pic18f2610 000000h-00ffffh (64k) pic18f2620 pic18f2680 PIC18F4610 pic18f4620 pic18f4680 000000h 1fffffh 3fffffh 01ffffh note: sizes of memory areas are not to scale. code memory unimplemented read as ? 0 ? configuration and id space memory size/device 64 kbytes (pic18fx6x0) 48 kbytes (pic18fx5x5) address range boot block boot block 000000h 0007ffh block 0 block 0 000800h 003fffh block 1 block 1 004000h 007fffh block 2 block 2 008000h 00bfffh block 3 unimplemented read ? 0 ?s 00c000h 00ffffh unimplemented read ? 0 ?s 01ffffh ? 2004 microchip technology inc. ds39622a-page 7 pic18fx5x5/x6x0 in addition to the code memory space, there are three blocks in the configuration and id space that are acces- sible to the user through table reads and table writes. their locations in the memory map are shown in figure 2-6. users may store identification information (id) in eight id registers. these id registers are mapped in addresses 200000h through 200007h. the id locations read out normally, even after code protection is applied. locations 300000h through 30000dh are reserved for the configuration bits. these bits select various device options and are described in section 5.0 ?configura- tion word? . these configuration bits read out normally, even after code protection. locations 3ffffeh and 3fffffh are reserved for the device id bits. these bits may be used by the program- mer to identify what device type is being programmed and are described in section 5.0 ?configuration word? . these device id bits read out normally, even after code protection. 2.3.1 memory address pointer memory in the address space, 0000000h to 3fffffh, is addressed via the table pointer register, which is comprised of three pointer registers: tblptru, at ram address 0ff8h tblptrh, at ram address 0ff7h tblptrl, at ram address 0ff6h the 4-bit command, ? 0000 ? (core instruction), is used to load the table pointer prior to using many read or write operations. figure 2-6: config uration and id locations fo r pic18fx5x5/x6x0 devices tblptru tblptrh tblptrl addr[21:16] addr[15:8] addr[7:0] id location 1 200000h id location 2 200001h id location 3 200002h id location 4 200003h id location 5 200004h id location 6 200005h id location 7 200006h id location 8 200007h config1l 300000h config1h 300001h config2l 300002h config2h 300003h config3l 300004h config3h 300005h config4l 300006h config4h 300007h config5l 300008h config5h 300009h config6l 30000ah config6h 30000bh config7l 30000ch config7h 30000dh device id1 3ffffeh device id2 3fffffh note: sizes of memory areas are not to scale. 000000h 1fffffh 3fffffh 01ffffh code memory unimplemented read as ? 0 ? configuration and id space 2fffffh pic18fx5x5/x6x0 ds39622a-page 8 ? 2004 microchip technology inc. 2.4 high-level overview of the programming process figure 2-8 shows the high-level overview of the programming process. first, a bulk erase is performed. next, the code memory, id locations and data eeprom (pic18fxx2x and pic18fxx8x only) are programmed. these memories are then verified to ensure that programming was successful. if no errors are detected, the configuration bits are then programmed and verified. 2.5 entering high-voltage icsp program/verify mode the high-voltage icsp program/verify mode is entered by holding pgc and pgd low and then raising mclr /v pp to v ihh (high voltage). once in this mode, the code memory, data eeprom (pic18fxx2x and pic18fxx8x only), id locations and configuration bits can be accessed and programmed in serial fashion. the sequence that enters the device into the program/ verify mode places all unused i/os in the high-impedance state. 2.5.1 entering low-voltage icsp program/verify mode when the lvp configuration bit is ? 1 ? (see section 5.3 ?single-supply icsp programming? ), the low- voltage icsp mode is enabled. low-voltage icsp program/verify mode is entered by holding pgc and pgd low, placing a logic high on pgm and then raising mclr /v pp to v ih . in this mode, the rb5/pgm pin is dedicated to the programming function and ceases to be a general purpose i/o pin. the sequence that enters the device into the program/ verify mode places all unus ed i/os in the high-impedance state. figure 2-7: entering high-voltage program/verify mode figure 2-8: high-level programming flow figure 2-9: entering low-voltage program/verify mode mclr /v pp p12 pgd pgd = input pgc v dd d110 p13 p1 start program memory program ids program data ee verify program verify ids verify data program configuration bits verify configuration bits done perform bulk erase (pic18fxx2x and pic18fxx8x only) mclr /v pp p12 pgd pgd = input pgc pgm p15 v dd v ih v ih ? 2004 microchip technology inc. ds39622a-page 9 pic18fx5x5/x6x0 2.6 serial program/verify operation the pgc pin is used as a clock input pin and the pgd pin is used for entering command bits and data input/ output during serial operation. commands and data are transmitted on the rising edge of pgc, latched on the falling edge of pgc and are least significant bit (lsb) first. 2.6.1 4-bit commands all instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. to input a command, pgc is cycled four times. the commands needed for programming and verification are shown in table 2-3. depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. throughout this specification, commands and data are presented as illustrated in table 2-4. the 4-bit com- mand is shown msb first. the command operand, or ?data payload?, is shown pic18fx5x5/x6x0 ds39622a-page 10 ? 2004 microchip technology inc. 3.0 device programming programming includes the ability to erase or write the various memory regions within the device. in all cases except high-voltage icsp bulk erase, the eecon1 register must be configured in order to operate on a particular memory region. when using the eecon1 register to act on code mem- ory, the eepgd bit must be set (eecon1<7> = 1 ) and the cfgs bit must be cleared (eecon1<6> = 0 ). the wren bit must be set (eecon1<2> = 1 ) to enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. the free bit must be set (eecon1<4> = 1 ) in order to erase the program space being pointed to by the table pointer. the erase or write sequence is initiated by setting the wr bit (eecon1<1> = 1 ). it is strongly recommended that the wren bit only be set immediately prior to a program erase. 3.1 icsp erase 3.1.1 high-voltage icsp bulk erase erasing code or data eeprom is accomplished by configuring two bulk erase control registers located at 3c0004h and 3c0005h. code memory may be erased portions at a time, or the user may erase the entire device in one action. ?bulk erase? operations will also clear any code-protect settings associated with the memory block erased. erase options are detailed in table 3-1. if data eeprom is code-protected (cpd = 0 ), the user must request an erase of data eeprom (e.g., 0x84h as shown in table 3-1, where x defines the block to be erased). table 3-1: bulk erase options the actual bulk erase function is a self-timed opera- tion. once the erase has started (falling edge of the 4th pgc after the nop command), serial execution will cease until the erase completes (parameter p11). during this time, pgc may continue to toggle but pgd must be held low. the code sequence to erase the entire device is shown in table 3-2 and the flow chart is shown in figure 3-1. table 3-2: bulk erase command sequence figure 3-1: bulk erase flow description data chip erase 0f87h erase data eeprom (1) 0084h erase boot block 0081h erase config bits 0082h erase block 0 0180h erase block 1 0280h erase block 2 0480h erase block 3 0880h note 1: pic18fxx2x and pic18fxx8x only. note: a bulk erase is the only way to reprogram code-protect bits from an on-state to an off-state. 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 05 6e f6 0f 0f 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 87 87 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 05h movwf tblptrl write 0fh to 3c0005h movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 8787h to 3c0004h to erase entire device. nop hold pgd low until erase completes. start done write 8787h to 3c0004h to erase entire device write 0f0fh delay p11+p10 time to 3c0005h ? 2004 microchip technology inc. ds39622a-page 11 pic18fx5x5/x6x0 figure 3-2: bulk erase timing 3.1.2 low-voltage icsp bulk erase when using low-voltage icsp, the part must be sup- plied by the voltage specified in parameter #d111 if a bulk erase is to be executed. all other bulk erase details as described above apply. if it is determined that a program memory erase must be performed at a supply voltage below the bulk erase limit, refer to the erase methodology described in sections 3.1.3 and 3.2.1. if it is determined that a data eeprom (pic18fxx2x and pic18fxx8x only) erase must be performed at a supply voltage below the bulk erase limit, follow the methodology described in section 3.3 ?data eeprom programming (pic18fxx2x and pic18fxx8x only)? and write ? 1 ?s to the array. 3.1.3 icsp row erase regardless of whether high or low-voltage icsp is used, it is possible to erase one row (64 bytes of data), provided the block is not code or write-protected. rows are located at static boundaries beginning at program memory address 000000h, extending to the internal program memory limit (see section 2.3 ?memory map? ). the row erase duration is externally timed and is controlled by pgc. after the wr bit in eecon1 is set, a nop is issued, where the 4th pgc is held high for the duration of the programming time, p9. after pgc is brought low, the programming sequence is terminated. pgc must be held low for the time spec- ified by parameter p10 to allow high-voltage discharge of the memory array. the code sequence to row erase a pic18fx5x5/x6x0 device is shown in table 3-3. the flow chart shown in figure 3-3 depicts the logic necessary to completely erase a pic18fx5x5/x6x0 device. the timing diagram that details the ?start programming? command and parameters p9 and p10 is shown in figure 3-5. n 12 34 1 21516 123 pgc p5 p5a pgd pgd = input 0 0011 p11 p10 erase time 000000 12 00 4 0 1 2 15 16 p5 123 p5a 4 0000 n 4-bit command 4-bit command 4-bit command 16-bit data payload 16-bit data payload 16-bit data payload 11 note: the tblptr register can point at any byte within the row(s) intended for erase. pic18fx5x5/x6x0 ds39622a-page 12 ? 2004 microchip technology inc. table 3-3: erase code memory code sequence figure 3-3: single row erase code memory flow 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 0000 8e a6 9c a6 84 a6 bsf eecon1, eepgd bcf eecon1, cfgs bsf eecon1, wren step 2: point to first row in code memory. 0000 0000 0000 6a f8 6a f7 6a f6 clrf tblptru clrf tblptrh clrf tblptrl step 3: enable erase and erase single row. 0000 0000 0000 88 a6 82 a6 00 00 bsf eecon1, free bsf eecon1, wr nop - hold pgc high for time p9. step 4: repeat step 3, with address pointer incremented by 64 until all rows are erased. done start delay p9 + p10 time for erase to occur all rows done? no yes addr = 0 configure device for row erases addr = addr + 64 start erase sequence and hold pgc high until done ? 2004 microchip technology inc. ds39622a-page 13 pic18fx5x5/x6x0 3.2 code memory programming programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. the write buffer is 64 bytes in size and can be mapped to any 64-byte area in code memory beginning at location 000000h. the actual memory write sequence takes the contents of this buffer and programs the 64-byte code memory region that contains the table pointer. the programming duration is externally timed and is controlled by pgc. after a ?start programming? com- mand is issued (4-bit command, ? 1111 ?), a nop is issued, where the 4th pgc is held high for the duration of the programming time, p9. after pgc is brought low, the programming sequence is terminated. pgc must be held low for the time spec- ified by parameter p10 to allow high-voltage discharge of the memory array. the code sequence to program a pic18fx5x5/x6x0 device is shown in table 3-4. the flow chart shown in figure 3-4 depicts the logic necessary to completely write a pic18fx5x5/x6x0 device. the timing diagram that details the ?start programming? command and parameters p9 and p10 is shown in figure 3-5. table 3-4: write code memory code sequence note: the tblptr register must point to the same 64-byte region when initiating the programming sequence as it did when the write buffers were loaded. 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 8e a6 9c a6 bsf eecon1, eepgd bcf eecon1, cfgs step 2: load write buffer. 0000 0000 0000 0000 0000 0000 0e pic18fx5x5/x6x0 ds39622a-page 14 ? 2004 microchip technology inc. figure 3-4: program code memory flow figure 3-5: table write and start programming instruction timing ( 1111 ) start write sequence all locations done? no done start yes delay p9+p10 time for write to occur load 2 bytes to write buffer at ? 2004 microchip technology inc. ds39622a-page 15 pic18fx5x5/x6x0 3.2.1 modifying code memory the previous programming example assumed that the device has been bulk erased prior to programming (see section 3.1.1 ?high-voltage icsp bulk erase? ). it may be the case, however, that the user wishes to modify only a section of an already programmed device. in this case, 64 bytes must be read out of code memory (as described in section 4.2 ?verify code memory and id locations? ) and buffered. modifications can be made on this buffer. then, the 64-byte block of code memory that was read out must be erased and rewritten with the modified data. the wren bit must be set if the wr bit in eecon1 is used to initiate a write sequence. table 3-5: modifying code memory 4-bit command data payload core instruction step 1: direct access to code memory. step 2: read and modify code memory (see section 4.1 ?read code memory, id locations and configuration bits? ). 0000 0000 8e a6 9c a6 bsf eecon1, eepgd bcf eecon1, cfgs step 3: set the table pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0e pic18fx5x5/x6x0 ds39622a-page 16 ? 2004 microchip technology inc. 3.3 data eeprom programming (pic18fxx2x and pic18fxx8x only) data eeprom is accessed one byte at a time via an address pointer (register pair eeadrh:eeadr) and a data latch (eedata). data eeprom is written by loading eeadrh:eeadr with the desired memory location, eedata with the data to be written and initiat- ing a memory write by appropriately configuring the eecon1 register. a byte write automatically erases the location and writes the new data (erase-before-write). when using the eecon1 register to perform a data eeprom write, both the eepgd and cfgs bits must be cleared (eecon1<7:6> = 00 ). the wren bit must be set (eecon1<2> = 1 ) to enable writes of any sort and this must be done prior to initiating a write sequence. the write sequence is initiated by setting the wr bit (eecon1<1> = 1 ). the write begins on the falling edge of the 4th pgc after the wr bit is set. it ends when the wr bit is cleared by hardware. after the programming sequence terminates, pgc must still be held low for the time specified by parame- ter p10 to allow high-voltage discharge of the memory array. figure 3-6: program data flow figure 3-7: data eeprom write timing start start write set data done no yes done ? enable write sequence set address wr bit clear? no yes n pgc pgd pgd = input 0000 bsf eecon1, wr 4-bit command 12 34 1 21516 p5 p5a p10 12 n poll wr bit, repeat until clear 16-bit data payload 12 3 4 1 21516 123 p5 p5a 4 1 2 15 16 p5 p5a 0000 movf eecon1, w, 0 4-bit command 0000 4-bit command shift out data movwf tablat pgc pgd (see below) (see figure 4-6) pgd = input pgd = output poll wr bit p11a ? 2004 microchip technology inc. ds39622a-page 17 pic18fx5x5/x6x0 table 3-6: programming data memory 4-bit command data payload core instruction step 1: direct access to data eeprom. 0000 0000 9e a6 9c a6 bcf eecon1, eepgd bcf eecon1, cfgs step 2: set the data eeprom address pointer. 0000 0000 0000 0000 0e pic18fx5x5/x6x0 ds39622a-page 18 ? 2004 microchip technology inc. 3.4 id location programming the id locations are programmed much like the code memory. the id registers are mapped in addresses 200000h through 200007h. these locations read out normally even after code protection. table 3-7 demonstrates the code sequence required to write the id locations. in order to modify the id locations, refer to the method- ology described in section 3.2.1 ?modifying code memory? . as with code memory, the id locations must be erased before modified. table 3-7: write id sequence note: the user only needs to fill the first 8 bytes of the write buffer in order to write the id locations. 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 8e a6 9c a6 bsf eecon1, eepgd bcf eecon1, cfgs step 2: load write buffer with 8 bytes and write. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0e 20 6e f8 0e 00 6e f7 0e 00 6e f6 ? 2004 microchip technology inc. ds39622a-page 19 pic18fx5x5/x6x0 3.5 boot block programming the code sequence detailed in table 3-4 should be used, except that the address data used in ?step 2? will be in the range of 000000h to 0007ffh. 3.6 configuration bits programming unlike code memory, the configuration bits are pro- grammed a byte at a time. the ?table write, begin programming? 4-bit command ( 1111 ) is used, but only 8 bits of the following 16-bit payload will be written. the lsb of the payload will be written to even addresses and the msb will be written to odd addresses. the code sequence to program two consecutive configuration locations is shown in table 3-8. table 3-8: set address pointer to configuration location figure 3-8: configurat ion programming flow note: the address must be explicitly written for each byte programmed. the addresses can not be incremented in this mode. 4-bit command data payload core instruction step 1: enable writes and direct access to config memory. 0000 0000 8e a6 8c a6 bsf eecon1, eepgd bsf eecon1, cfgs step 2 (1) : set table pointer for config byte to be written. write even/odd addresses. 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 0e 30 6e f8 0e 00 6e f7 0e 00 6e f6 pic18fx5x5/x6x0 ds39622a-page 20 ? 2004 microchip technology inc. 4.0 reading the device 4.1 read code memory, id locations and configuration bits code memory is accessed one byte at a time via the 4-bit command, ? 1001 ? (table read, post-increment). the contents of memory pointed to by the table pointer (tblptru:tblptrh:tblptrl) is serially output on pgd. the 4-bit command is shifted in lsb first. the read is executed during the next 8 clocks, then shifted out on pgd during the last 8 clocks, lsb to msb. a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-1). this operation also increments the table pointer pointer by one, pointing to the next byte in code memory for the next read. this technique will work to read any memory in the 000000h to 3fffffh address space, so it also applies to the reading of the id and configuration registers. table 4-1: read code memory sequence figure 4-1: table read post-increment instruction timing ( 1001 ) 4-bit command data payload core instruction step 1: set table pointer. 0000 0000 0000 0000 0000 0000 0e ? 2004 microchip technology inc. ds39622a-page 21 pic18fx5x5/x6x0 4.2 verify code memory and id locations the verify step involves reading back the code memory space and comparing it against the copy held in the programmer?s buffer. memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer?s buffer. refer to section 4.1 ?read code memory, id locations and configuration bits? for implementation details of reading code memory. the table pointer must be manually set to 200000h (base address of the id locations) once the code memory has been verified. the post-increment feature of the table read 4-bit command may not be used to increment the table pointer beyond the code memory space. in a 64-kbyte device, for example, a post- increment read of address ffffh will wrap the table pointer back to 000000h, rather than point to unimplemented address 010000h. figure 4-2: verify code memory flow read low byte read high byte does word = expect data? failure, report error all code memory verified? no yes no set pointer = 0 start set pointer = 200000h yes read low byte read high byte does word = expect data? failure, report error all id locations verified? no yes done yes no with post-increment with post-increment increment pointer pic18fx5x5/x6x0 ds39622a-page 22 ? 2004 microchip technology inc. 4.3 verify configuration bits a configuration address may be read and output on pgd via the 4-bit command, ? 1001 ?. configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. the result may then be immediately compared to the appropriate configuration data in the programmer?s memory for verification. refer to section 4.1 ?read code memory, id locations and configuration bits? for implementation details of reading configuration data. 4.4 read data eeprom memory data eeprom is accessed one byte at a time via an address pointer (register pair eeadrh:eeadr) and a data latch (eedata). data eeprom is read by loading eeadrh:eeadr with the desired memory location and initiating a memory read by appropriately configur- ing the eecon1 register. the data will be loaded into eedata, where it may be serially output on pgd via the 4-bit command, ? 0010 ? (shift out data holding reg- ister). a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-4). the command sequence to read a single byte of data is shown in table 4-2. figure 4-3: read data eeprom flow table 4-2: read data eeprom memory start set address read byte done no yes done ? move to tablat shift out data 4-bit command data payload core instruction step 1: direct access to data eeprom. 0000 0000 9e a6 9c a6 bcf eecon1, eepgd bcf eecon1, cfgs step 2: set the data eeprom address pointer. 0000 0000 0000 0000 0e ? 2004 microchip technology inc. ds39622a-page 23 pic18fx5x5/x6x0 figure 4-4: shift out data holding register timing ( 0010 ) 4.5 verify data eeprom a data eeprom address may be read via a sequence of core instructions (4-bit command, ? 0000 ?) and then output on pgd via the 4-bit command, ? 0010 ? (shift out data holding register). the result may then be immediately compared to the appropriate data in the programmer?s memory for verification. refer to section 4.4 ?read data eeprom memory? for implementation details of reading data eeprom. 4.6 blank check the term ?blank check? means to verify that the device has no programmed memory cells. all memories must be verified: code memory, data eeprom, id locations and configuration bits. the device id registers (3ffffeh:3fffffh) should be ignored. a ?blank? or ?erased? memory cell will read as a ? 1 ?. so, ?blank checking? a device merely means to verify that all bytes read as ffh except the configuration bits. unused (reserved) configuration bits will read ? 0 ? (pro- grammed). refer to table 5-2 for blank configuration expect data for the various pic18fx5x5/x6x0 devices. given that ?blank checking? is merely code and data eeprom verification with ffh expect data, refer to section 4.4 ?read data eeprom memory? and section 4.2 ?verify code memory and id locations? for implementation details. figure 4-5: blank check flow 1234 pgc p5 pgd pgd = input shift data out p6 pgd = output 5678 1234 p5a 91011 13 1516 14 12 fetch next 4-bit command 0100 pgd = input lsb msb 12 34 56 12 34 nnnn p14 yes no start blank check device is device blank? continue abort pic18fx5x5/x6x0 ds39622a-page 24 ? 2004 microchip technology inc. 5.0 configuration word the pic18fx5x5/x6x0 devices have several configu- ration words. these bits can be set or cleared to select various device configurations. all other memory areas should be programmed and verified prior to setting con- figuration words. these bits may be read out normally, even after read or code-protected. 5.1 id locations a user may store identification information (id) in eight id locations mapped in 200000h:200007h. it is recom- mended that the most significant nibble of each id be 0fh. in doing so, if the user code inadvertently tries to execute from the id space, the id data will execute as a nop . 5.2 device id word the device id word for the pic18fx5x5/x6x0 devices is located at 3ffffeh:3fffffh. these bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read-protected. 5.3 single-supply icsp programming the lvp bit in configuration register, config4l, enables single-supply (low-voltage) icsp programming. the lvp bit defaults to a ? 1 ? from the factory. if single-supply programming mode is not used, the lvp bit can be programmed to a ? 0 ? and rb5/pgm becomes a digital i/o pin. however, the lvp bit may only be programmed by entering the high-voltage icsp mode, where mclr /v pp is raised to v ihh . once the lvp bit is programmed to a ? 0 ?, only the high-voltage icsp mode is available and only the high-voltage icsp mode can be used to program the device. table 5-1: device id value note 1: the normal icsp mode is always avail- able, regardless of the state of the lvp bit, by applying v ihh to the mclr /v pp pin. 2: while in low-voltage icsp mode, the rb5 pin can no longer be used as a general purpose i/o. device device id value devid2 devid1 pic18f2515 0ch 111x xxxx pic18f2525 0ch 110x xxxx pic18f2585 0eh 111x xxxx pic18f4515 0ch 011x xxxx pic18f4525 0ch 010x xxxx pic18f4585 0eh 101x xxxx pic18f2610 0ch 101x xxxx pic18f2620 0ch 100x xxxx pic18f2680 0eh 110x xxxx PIC18F4610 0ch 001x xxxx pic18f4620 0ch 000x xxxx pic18f4680 0eh 100x xxxx note: the ? x ?s in devid1 contain the device revision code. ? 2004 microchip technology inc. ds39622a-page 25 pic18fx5x5/x6x0 table 5-2: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ieso fcmen ? ? fosc3 fosc2 fosc1 fosc0 00-- 0111 300002h config2l ? ? ? borv1 borv0 boren1 boren0 pwrten ---1 1111 300003h config2h ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten ---1 1111 300005h config3h mclre ? ? ? ? lpt1osc pbaden ccp2mx 1--- -011 ? (2) 1--- -01- (2) 300006h config4l debug xinst ? ? ?lvp ?stvren 10-- -1-1 300008h config5l ? ? ? ? cp3 cp2 cp1 cp0 ---- 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l ? ? ? ? wrt3 wrt2 wrt1 wrt0 ---- 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ? ? ? ? ebtr3 ebtr2 ebtr1 ebtr0 ---- 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 (1) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (1) 3fffffh devid2 (1) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 1100 (3) 0000 1110 (2) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded cells are unimplemented, read as ? 0 ?. note 1: devid registers are read-only and c annot be programmed by the user. 2: pic18fxx8x devices only. 3: pic18fxx1x and pic18fxx2x devices only. pic18fx5x5/x6x0 ds39622a-page 26 ? 2004 microchip technology inc. 5.4 embedding configuration word information in the hex file to allow portability of code, a pic18fx5x5/x6x0 programmer is required to read the configuration word locations from the hex file. if configuration word information is not present in the hex file, then a simple warning message should be issued. similarly, while saving a hex file, all configuration word information must be included. an option to not include the configu- ration word information may be provided. when embedding configuration word information in the hex file, it should start at address 300000h. microchip technology inc. feels strongly that this feature is important for the benefit of the end customer. 5.5 embedding data eeprom information in the hex file to allow portability of code, a pic18fx5x5/x6x0 programmer is required to read the data eeprom information from the hex file. if data eeprom informa- tion is not present, a simple warning message should be issued. similarly, when saving a hex file, all data eeprom information must be included. an option to not include the data eeprom information may be provided. when embedding data eeprom information in the hex file, it should start at address f00000h. microchip technology inc. believes that this feature is important for the benefit of the end customer. 5.6 checksum computation the checksum is calculated by summing the following: the contents of all code memory locations the configuration word, appropriately masked id locations the least significant 16 bits of this sum are the checksum. table 5-3 (pages 27 through 32) describes how to calculate the checksum for each device. note: the checksum calculation differs depend- ing on the code-protect setting. since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. when calculating a checksum by reading a device, the entire code memory can simply be read and summed. the configuration word and id locations can always be read. ? 2004 microchip technology inc. ds39622a-page 27 pic18fx5x5/x6x0 table 5-3: checksum computation device code- protect checksum blank value 0xaa at 0 and max address pic18f2515 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+ sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+ (config1 & 00cf)+(config2 & 001f)+(config3 & 001f)+ (config4 & 0000)+(config5 & 0087)+(config6 & 00c5)+ (config7 & 0000)+(config8 & 000f)+(config9 & 00c0)+ (config10 & 000f)+(config11 & 00e0)+(config12 & 000f)+ (config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+ sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+ (config1 & 00cf)+(config2 & 001f)+(config3 & 001f)+ (config4 & 0000)+(config5 & 0087)+(config6 & 00c5)+ (config7 & 0000)+(config8 & 000f)+(config9 & 00c0)+ (config10 & 000f)+(config11 & 00e0)+(config12 & 000f)+ (config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 pic18f2525 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+ (config1 & 00cf)+(config2 & 001f)+(config3 & 001f)+ (config4 & 0000)+(config5 & 0087)+(config6 & 00c5)+ (config7 & 0000)+(config8 & 000f)+(config9 & 00c0)+ (config10 & 000f)+(config11 & 00e0)+(config12 & 000f)+ (config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 legend: item description cfgw = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and pic18fx5x5/x6x0 ds39622a-page 28 ? 2004 microchip technology inc. pic18f2585 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0465 03bb boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c34 0be9 boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+ (config1 & 00cf)+(config2 & 001f)+(config3 & 001f)+ (config4 & 0000)+(config5 & 0086)+(config6 & 00c5)+ (config7 & 0000)+(config8 & 000f)+(config9 & 00c0)+ (config10 & 000f)+(config11 & 00e0)+(config12 & 000f)+ (config13 & 0040)+sum(ids) 8431 83e6 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0425 042f pic18f2610 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 table 5-3: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description cfgw = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and ? 2004 microchip technology inc. ds39622a-page 29 pic18fx5x5/x6x0 pic18f2620 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 pic18f2680 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0465 03bb boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c34 0be9 boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8431 83e6 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0425 042f table 5-3: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description cfgw = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and pic18fx5x5/x6x0 ds39622a-page 30 ? 2004 microchip technology inc. pic18f4515 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 pic18f4525 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 table 5-3: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description cfgw = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and ? 2004 microchip technology inc. ds39622a-page 31 pic18fx5x5/x6x0 pic18f4585 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0465 03bb boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c34 0be9 boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8431 83e6 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0425 042f PIC18F4610 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 table 5-3: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description cfgw = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and pic18fx5x5/x6x0 ds39622a-page 32 ? 2004 microchip technology inc. pic18f4620 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0466 03bc boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c36 0beb boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0087)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8433 83e8 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0087)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0427 0431 pic18f4680 none sum(0000:07ff)+sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+ sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040) 0465 03bb boot block sum(0800:3fff)+sum(4000:7fff)+sum(8000:bfff)+sum(c000:ffff)+ (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0c34 0be9 boot/ block1/ block2 sum(8000:bfff)+sum(c000:ffff)+(config0 & 0000)+(config1 & 00cf)+ (config2 & 001f)+(config3 & 001f)+(config4 & 0000)+ (config5 & 0086)+(config6 & 00c5)+(config7 & 0000)+ (config8 & 000f)+(config9 & 00c0)+(config10 & 000f)+ (config11 & 00e0)+(config12 & 000f)+(config13 & 0040)+sum(ids) 8431 83e6 all (config0 & 0000)+(config1 & 00cf)+(config2 & 001f)+ (config3 & 001f)+(config4 & 0000)+(config5 & 0086)+ (config6 & 00c5)+(config7 & 0000)+(config8 & 000f)+ (config9 & 00c0)+(config10 & 000f)+(config11 & 00e0)+ (config12 & 000f)+(config13 & 0040)+sum(ids) 0425 042f table 5-3: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description cfgw = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and ? 2004 microchip technology inc. ds39622a-page 33 pic18fx5x5/x6x0 6.0 ac/dc characteristics timing requirements for program/verify test mode note 1: do not allow excess time when transitioning mclr between v il and v ihh ; this can cause spurious program executions to occur. the maximum transition time is: 1 t cy + t pwrt (if enabled) + 1024 t osc (for lp, hs, hs/pll and xt modes only) + 2 ms (for hs/pll mode only) + 1.5 s (for ec mode only) where t cy is the instruction cycle time, t pwrt is the power-up timer period, and t osc is the oscillator period. for specific values, refer to the electrical characteristics section of the device data sheet for the particular device. standard operating conditions operating temperature: 25 c is recommended param no. sym characteristic min max units conditions d110 v ihh high-voltage programming voltage on mclr /v pp 9.00 13.25 v d110a v ihl low-voltage programming voltage on mclr /v pp 2.00 5.50 v d111 v dd supply voltage during programming 2.00 5.50 v normal programming 4.50 5.50 v bulk erase operations d112 i pp programming current on mclr /v pp ?300 a d113 i ddp supply current during programming ? 10 ma d031 v il input low voltage v ss 0.2 v dd v d041 v ih input high voltage 0.8 v dd v dd v d080 v ol output low voltage ? 0.6 v i ol = 8.5 ma @ 4.5v d090 v oh output high voltage v dd ? 0.7 ? v i oh = -3.0 ma @ 4.5v d012 c io capacitive loading on i/o pin (pgd) ? 50 pf to meet ac specifications p1 t r mclr /v pp rise time to enter program/verify mode ?1.0 s (note 1) p2 t pgc serial clock (pgc) period 100 ? ns v dd = 5.0v 1? sv dd = 2.0v p2a t pgcl serial clock (pgc) low time 40 ? ns v dd = 5.0v 400 ? ns v dd = 2.0v p2b t pgch serial clock (pgc) high time 40 ? ns v dd = 5.0v 400 ? ns v dd = 2.0v p3 t set 1 input data setup time to serial clock 15 ? ns p4 t hld 1 input data hold time from pgc 15 ? ns p5 t dly 1 delay between 4-bit command and command operand 40 ? ns p5a t dly 1 a delay between 4-bit command operand and next 4-bit command 40 ? ns p6 t dly 2 delay between last pgc of command byte to first pgc of read of data word 20 ? ns p9 t dly 5 pgc high time (minimum programming time) 1 ? ms p10 t dly 6 pgc low time after programming (high-voltage discharge time) 40 ? s p11 t dly 7 delay to allow self-timed data write or bulk erase to occur 5?ms p11a t drwt data write polling time 4 ? ms p12 t hld 2 input data hold time from mclr /v pp 2? s p13 t set 2v dd setup time to mclr /v pp 100 ? ns p14 t valid data out valid from pgc 10 ? ns p15 t set 3pgm setup time to mclr /v pp 2? s pic18fx5x5/x6x0 ds39622a-page 34 ? 2004 microchip technology inc. notes: ds39622a-page 35 ? 2004 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval, smartshunt and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartt el and total endurance are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semicondu ctor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving t he code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds39622a-page 36 ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 san jose 1300 terra bella avenue mountain view, ca 94043 tel: 650-215-1444 fax: 650-961-0286 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 706b wan tai bei hai bldg. no. 6 chaoyangmen bei str. beijing, 100027, china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building, no. 2 fengxiangnan road, ronggui town, shunde district, foshan city, guangdong 528303, china tel: 86-757-28395507 fax: 86-757-28395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 01/26/04 w orldwide s ales and s ervice |
Price & Availability of PIC18F4610
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |